The present invention relates to a method of testing for stuck-at faults of a synchronous sequential circuit. When an electronics circuit comprising a synchronous circuit for use in a partial-scan method or non-scan is manufactured, it is tested for a stuck-at fault in which a logic value of a signal line in the circuit is permanently stuck at "1" or "0".
As shown in FIG. 1, a partial scan circuit has a memory element portion which includes non-scan registers and scan registers.
The non-scan registers are treated as pure internal registers and, except for initialization, the input or output value of registers can be set or observed indirectly through the operation of the sequential circuit.
The scan registers, also internal, are simultaneously connected by a test path. It is possible to set or observe the value of the scan register from a test terminal. A testing sequence comprises a setting of a scan register, values, (scan-in), a setting of the primary input, a clocking of the system clock, an observation of the primary output and an observation of the scan register values (scan-out). A full scan circuit does not include non-scan registers and thus can apply a method adopted to a combinational circuit to a test pattern generation. However, in the partial scan circuit, it is necessary to apply a method adapted for a sequential circuit to a test pattern generation. In the full scan circuit, one test pattern is sufficient for detecting one fault. In contrast, in the partial scan circuit, a test pattern sequence becomes necessary for each fault, i.e., the sequential circuit must be expanded in a time direction or extended over time.
The non-scan circuit does not have any scan registers in the partial scan circuit. Therefore, it naturally requires a method adapted for a sequential circuit, such as extending the sequential circuit in a time direction, and requires a time sequence test pattern when the test pattern is generated.
The present invention is directed to a non-scan circuit and a partial-scan circuit and therefore, when the test pattern is generated, the sequential circuit is extended in a time direction.
A defective item in a circuit product including the sequential circuit is specified as the result of the test, and the reliability of the circuit product can be raised by removing the defective item. A test for a stuck-at fault of a sequential circuit, i.e., a synchronous circuit, is performed, in the case of a full scan method, by inputting a scan-in signal into and outputting a scan-out signal from a scan path comprising all the memory elements provided in the synchronous circuit. When a partial scan or non-scan method is used instead of a full scan, some memory elements are not scanned. Thus, in order to test a memory element which has not been scanned, the synchronous circuit should be expanded into a plurality of combinational circuits over time. Specifically, a test pattern generation for a stuck-at fault of a synchronous circuit for use in a non-scan or a partial scan method is performed by expanding the synchronous circuit into a plurality of combinational circuits which are aligned along the time axis. Consequently, a process of time expansion is performed, and test patterns for respective combinational circuits are formed by examining the non-detected faults of respective combinational circuits, thereby performing a process of generating test patterns. Moreover, a primary output of a combinational circuit is observed after supplying respective test patterns to the corresponding combinational circuit sequentially.
FIG. 2A shows a simplified model of a synchronous circuit for use in a non-scan or a partial scan method which comprises a combinational circuit part (C)1 and a memory part (M)2.
A primary input PI is provided to the combinational circuit 1 and a feedback loop is formed between the combinational circuit part 1 and the memory element part 2. A primary output PO is obtained from the combinational circuit part 1.
FIG. 2B is a conceptual view showing the iterative expansion of the model. In order to break the feedback loop shown in FIG. 1, combinational circuits 34 (c1, c2 . . . ct-1, ct0, ct+1 . . . ) are generated at respective times ti (i=i1, i2 . . . it-1, it0, it+1 . . . ). External inputs i1, i2 . . . it-1, it0, it+1 . . . and primary outputs o1, o2 . . . ot-1, ot0, ot+1 . . . of combinational circuits 34 (c1, c2 . . . ct-1, ct0, ct+1 . . . ) at respective times t form primary input PI and primary output PO in the model shown in FIG. 2B.
All flip-flops are replaced by the equivalent logic gates and the D flip-flop has its affirmative output replaced simply by a signal line and its negative output by an inverter.
As a result, a combinational circuit having the same operation as the synchronous circuit shown in FIG. 2A is constructed. Usually, the subject of a test is a single fault, but multiple faults may be the subject of the test when this expansion of a synchronous circuit is performed.
When the model is expanded over time, as described above, then after multiple faults are inserted, test pattern generation algorithms for combinational circuits, for example, the D algorithm or PODEM method, are applied to obtain input values of the circuit and to provide the input values in a time series again. This forms a test pattern to be input to the primary input i1, i2 . . . . it-1, it0, it+1 of the model.
Respective input values (i1, i2 . . . it-1, it0, it+1 . . . ) of the test pattern are applied to the corresponding combinational circuit 34 (c1, c2 . . . ct-1, ct0, ct+1 . . . . ) at respective times and the primary outputs (o1, o2 . . . . or-1, ot0, ot+1 . . . . ) of the combinational circuit 34 (c1, c2 . . . ct-1, ct0, ct+1 . . . ) are observed at the respective times t, so that the existence of a fault may be determined.
When a test pattern is obtained for a particular fault, a sequence of pattern setting, clocking, and output value observation is repeated a number of times equal to the number of patterns after the memory element is initialized, as shown in FIG. 3.
FIGS. 4A and 4B show generation of a test pattern with more specificity. By performing a repeated expansion of the circuit shown in FIG. 4A, three combinational circuits 34 which are aligned along the time axis, as shown in FIG. 4B, are formed.
When test pattern generation algorithms for combinational circuits, for example, the D algorithm or PODEM method, are applied to this circuit for the purpose of detecting a fault at time t, i.e., a single fault at the input of the inverter, an input value (x, 1, 1) is obtained and the output value is x, D. The same process is performed for times t-1 and t+1 to set the value "1" at the input and provide the output D to the external unit. Then, input values (x, x, D) and (0, 1, D) are respectively obtained.
In this case, the condition required for the flip-flop value at time t-1 is satisfied regardless of the initial value of D-FF (D-Flipflop) 4; thus, this is determined to be the initial state.
Further, the above test pattern is provided in a time series and a final test pattern, in which the input pattern becomes (x, x), (x, 1), (0, 1) at respective times 0, 1 and 2, is produced with respect to the fault in question. More specifically, a single fault at the input of the inverter.
In order to perform a test for multiple faults which covers all the faults of a circuit, the process recited above is performed for respective faults. Then, the scale of a subject circuit becomes several times that of the synchronous circuit due to the iterative expansion and thus, the volume of processing for the circuit under test becomes extremely large.
Therefore, when a test pattern for a particular fault is obtained, a fault simulation is performed to obtain all the faults that can be detected simultaneously by the same test pattern. Then, the fault test is performed. The same process is repeated for the following tests and is repeated to find faults which have not yet been detected, as shown in FIG. 3.
When an iterative expansion is performed with regard to the synchronous circuit for use with a non-scan method, the circuit scale after expansion becomes more than several times that before expansion and the volume of processing for generating the test patterns increases exponentially with the increase of the circuit scale in the worst case and increases, on the order of a power of two in the average case, with the circuit scale. Thus, the volume of processing becomes several tens or several hundreds of times that for a combinational circuit.
With an increase of the circuit scale, the number of selections occurring during the generation of the test patterns increases and the number of back tracks increases. As a result, the processing time per fault is increased. As the time for testing may be limited, the test is often stopped before completion if a large scale is involved. Therefore, many faults which could, in theory, be detected remain undetected.
For a synchronous circuit for use in a partial scan method, some of the memory element values can be replaced by a scan register which can be accessed externally. Thus, the ease of observation and control of the partial scan for a synchronous circuit is improved compared to a non-scan synchronous circuit.
However, the partial scan circuit includes many non-scanned memory elements and therefore, in the case of a large scale circuit, an extensive amount of time is required for generating test patterns. Consequently, it becomes difficult to raise the fault detection ratio due to the limitation of the test time.